1. Field of the Invention
This invention relates to a non-volatile memory, and more particularly to a non-volatile memory programmable by applying a predetermined amount of programmed voltage to cause an insulation breakdown to allow said memory to irreversibly conduct electricity.
2. Description of the Prior Art
Conventional counterparts of non-volatile memories are constituted of cells each incorporating two devices; one transistor and one anti-fuse. As shown in FIG. 5 (a) and FIG. 5 (b), on a silicon substrate 31 having a device isolation insulating film 32, an activated region 31' and an oxide film 33 on said region, a gate electrode 34 acting as a word line, a source region 35 and a drain region 36 are formed to constitute together a transistor, which acts as a select transistor. On the drain region 36, a fuse insulating film 37 thinner in thickness than an oxide film in other regions is formed in the place of the oxide film 33. In addition, an electrode polysilicon layer 38 acting as a bit line is formed to overlay the silicon substrate 31 and the gate electrode 34. The fuse insulating film 37 and the electrode polysilicon layer 38 constitute an anti-fuse device. Energizing a select transistor and applying voltage to a preselected bit line causes an insulation breakdown in the fuse insulating film 37 of a preselected cell, thereby allowing the film to irreversibly conduct electricity.
When writing in memory contents onto the non-volatile memory, voltage is applied to a gate electrode 34 of the select transistor acting as a word line to energize the select transistor. Besides, energizing the polysilicon layer 38 acting as a bit line at a voltage higher than in reading memory contents causes an insulation breakdown in the fuse insulating film 37 to electrify a channel region of the select transistor from the bit line to the source region 35.
It is known that the larger the amount of electric current applied in writing in memory contents is, the smaller resistance the above conventional non-volatile memories have in reading them (See Dielectric Based on Anti-Fuse For Logic and Memory ICs (IEDM '88). Besides, in the above mentioned non-volatile memory, since the select transistor and the anti-fuse are connected in series in operation, the select transistor controls electric current both in reading and writing in memory contents.
The electric currents are represented by the following equation as a drain electric current; EQU I.sub.D =1/2.multidot.W/L.multidot.Meff.multidot.C.sub.OM (V.sub.GS -V.sub.th)
wherein W represents a gate width, L a gate length, Meff mobility, C.sub.OM a gate capacity, V.sub.GS a gate voltage and V.sub.th threshold voltage. The equation designates that two methods are available for increasing the electric current conducting the non-volatile memory; one is to enlarge the gate width of the select transistor and the other is to shrink the gate length. However, enlarging the gate width demands a larger memory size while shrinking the gate length induces a reduction in dielectric strength in the select transistor. It naturally follows that a preferable type of the non-volatile memory cannot be easily embodied in the prior art.